System and method of designing integrated circuit by considering local layout effect

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United States of America Patent

PATENT NO 10817637
APP PUB NO 20180032658A1
SERIAL NO

15643472

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Abstract

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A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.

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Patent Owner(s)

Patent OwnerAddress
SAMSUNG ELECTRONICS CO LTDGYEONGGI DO SOUTH KOREA GYEONGGI-DO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ha, Naya Seoul, KR 4 34
Jeong, Kwang-ok Hwaseong-si, KR 9 46
Kim, Hyung-ock Seoul, KR 10 98
Kim, Jae-hoon Seoul, KR 202 1846
Kim, Yong-Durk Hwaseong-si, KR 4 16
Lee, Bong-hyun Suwon-si, KR 12 89

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