Real time memory address translation device
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United States of America Patent
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Jun 25, 2019
Grant Date -
Feb 1, 2018
app pub date -
Oct 10, 2016
filing date -
Jul 31, 2016
priority date (Note) -
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Abstract
A real time memory address translation device is described herein. The address translation device operates to change memory addresses from one address space that is used by system buses to another address space that is used by a main memory of the associated system. The translation device may be placed on the same chip as a corresponding processor core, for example, on a system on chip. The on-chip arrangement of the translation device enables predictable translation times to meet real-time requirement of time-sensitive subsystems.
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