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• 15 United States
• 10 France
• 8 Japan
• 7 China
• 5 Korea
• 2 Other

Patent Owner(s)

Patent Owner	Address
INTEL CORPORATION	2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

International Classification(s)

• G06F:ELECTRIC DIGITAL DATA PROCESSING

• 2016 Application Filing Year
• G06F Class
• 60255 Applications Filed
• 46180 Patents Issued To-Date
• 76.65 % Issued To-Date

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
KUMAR, Mohan J	Aloha, US	231	3360
# of filed Patents : 231 Total Citations : 3360
LIU, Min	Portland, US	296	2713
# of filed Patents : 296 Total Citations : 2713
LUO, Zhenlin	Beijing, CN	1	12
# of filed Patents : 1 Total Citations : 12
NACHIMUTHU, Murugasamy K	Beaverton, US	120	1269
# of filed Patents : 120 Total Citations : 1269
VERGIS, George	Portland, US	142	975
# of filed Patents : 142 Total Citations : 975
ZWISLER, Ross E	Lafayette, US	17	166
# of filed Patents : 17 Total Citations : 166

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Patent Citation Ranking

• 12 Citation Count
• G06F Class

• 82.01 % this patent is cited more than
• 7 Age

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Full Text

US Patent Application No: 2018/0032,429

TECHNIQUES TO ALLOCATE REGIONS OF A MULTI-LEVEL, MULTI-TECHNOLOGY SYSTEM MEMORY TO APPROPRIATE MEMORY ACCESS INITIATORS

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Abstract

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A method is described. The method includes recognizing different latencies and/or bandwidths between different levels of a system memory and different memory access requestors of a computing system. The system memory includes the different levels and different technologies. The method also includes allocating each of the memory access requestors with a respective region of the system memory having an appropriate latency and/or bandwidth.

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Description

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Claims

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