THREE SOURCE OPERAND FLOATING-POINT ADDITION INSTRUCTION WITH OPERAND NEGATION BITS AND INTERMEDIATE AND FINAL RESULT ROUNDING
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
N/A
app pub date -
Oct 9, 2017
filing date -
Mar 26, 2014
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A processor of an aspect includes a decode unit to decode a three source floating point addition instruction indicating a first source operand having a first floating point data element, a second source operand having a second floating point data element, and a third source operand having a third floating point data element. An execution unit is coupled with the decode unit. The execution unit, in response to the instruction, stores a result in a destination operand indicated by the instruction. The result includes a result floating point data element that includes a first floating point rounded sum. The first floating point rounded sum represents an additive combination of a second floating point rounded sum and the third floating point data element. The second floating point rounded sum represents an additive combination of the first floating point data element and the second floating point data element.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully