POWER REDUCTION THROUGH CLOCK MANAGEMENT

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United States of America Patent

APP PUB NO 20180032307A1
SERIAL NO

15725813

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Power reduction through clock management techniques are disclosed. In one aspect, the clock management is applied to a clock signal on a SOUNDWIRE™ communication bus. In particular, a control system associated with a master device on the communication bus may evaluate frequency requirements of audio streams on the communication bus and select a lowest possible clock frequency that meets the frequency requirements. Lower clock frequencies result in fewer clock transitions and result in a net power saving relative to higher clock frequencies. In the event of a clock frequency change, the master device communicates the clock frequency that will be used prospectively to slave devices on the communication bus, and all devices transition to the new frequency at the same frame boundary. In addition to the power savings, exemplary aspects of the present disclosure do not impact an active audio stream.

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Patent Owner(s)

Patent OwnerAddress
QUALCOMM INCORPORATED5775 MOREHOUSE DRIVE SAN DIEGO CA 92121-1714

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Amarilio, Lior Yokneam, IL 75 656
Khazin, Alexander Nesher, IL 8 60

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