Stacked memory device and a memory chip including the same
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United States of America Patent
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Jun 25, 2019
Grant Date -
Feb 1, 2018
app pub date -
Jun 8, 2017
filing date -
Jul 26, 2016
priority date (Note) -
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Abstract
A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.
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