Semiconductor power and performance optimization
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United States of America Patent
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Feb 26, 2019
Grant Date -
Feb 1, 2018
app pub date -
Jul 27, 2016
filing date -
Jul 27, 2016
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Abstract
Embodiments are directed to a method and system for testing and optimizing integrated circuit devices. Latches within an integrated circuit device that fail to operate properly are found using observed data from a test. Thereafter, a directed graph of the layout of the integrated circuit is used to find clock controllers that feed into the latches. The clock controllers that are the most likely to be at issue are ranked, then testing can be performed to confirm that a critical path can be found. The critical path can be excluded from further power optimization to maintain the performance of the integrated circuit device. Other embodiments are also disclosed.
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