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United States of America Patent

SERIAL NO

15640893

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The present disclosure there is provided a pattern detection unit (300; 400) comprising a shift register (302; 402) configured to over-sample a multi-bit input signal such that each bit of the input signal is represented by a plurality of samples in the shift register (302; 402); and a correlator (304; 404) configured to compare a target pattern with two or more of the plurality of samples of each bit from the shift register (302; 402) in order to determine whether or not the input signal matches the target pattern.

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Patent Owner(s)

Patent OwnerAddress
NXP B VHIGH TECH CAMPUS 60 EINDHOVEN 5656 AG

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
PERISSAKIS, Stylianos Graz, AT 4 17
POSCH, Martin Graz, AT 8 106

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  • 1 Citation Count
  • H04M Class
  • 21.43 % this patent is cited more than
  • 7 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges741214831710771311810454201 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +010020030040050060070080090010001100120013001400150016001700180019002000210022002300

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