LDPC decoder, semiconductor memory system and operating method thereof
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United States of America Patent
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Oct 16, 2018
Grant Date -
Jan 25, 2018
app pub date -
May 19, 2017
filing date -
Jul 21, 2016
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Abstract
An operation method of a LPC decoder includes: initializing variable nodes of a Tanner graph representing a parity check matrix; performing a check node update to check nodes of the Tanner graph based on variable node values of the variable nodes; performing a variable node update when there are USC nodes among the updated check nodes as a result of the check node update; and repeating the performing of the check node update and the variable node update when there are USC nodes as the result of the check node update, wherein the performing of the variable node update includes: selecting among the variable nodes a predetermined number of variable nodes having a USC value greater than a threshold; and flipping the variable node values of the selected variable nodes, and wherein the USC value is a number of the USC nodes linked to one of the variable nodes.
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