Technologies for performing low-latency decompression with tree caching

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United States of America Patent

PATENT NO 9954552
SERIAL NO

15473748

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Technologies for performing low-latency decompression include a managed node to parse, in response to a determination that a read tree descriptor does not match a cached tree descriptor, the read tree descriptor to construct one or more tables indicative of codes in compressed data. Each code corresponds to a different symbol. The managed node is further to decompress the compressed data with the one or more tables and store the one or more tables in association with the read tree descriptor in a cache memory for subsequent use.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cutter, Daniel F Maynard, US 43 562
Gopal, Vinodh Westborough, US 374 3055
Guilford, James D Northborough, US 152 1501
Yap, Kirk S Westborough, US 112 1130

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