Balancing delay associated with dual-edge trigger clock gaters
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United States of America Patent
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Jan 22, 2019
Grant Date -
Jan 25, 2018
app pub date -
Jul 22, 2016
filing date -
Jul 22, 2016
priority date (Note) -
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Abstract
Techniques are disclosed relating to dual-edge triggered (DET) clock gater circuitry. In some embodiments, an apparatus includes a first series of DET clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry. In some embodiments, ones of the DET clock gater circuits are controlled by respective control signals and are configured to maintain a mode indicator indicating whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock. In some embodiments, the apparatus also includes a first adjustable delay circuit configured to adjust delay imposed on the output clock signal from the first series of DET clock gater circuits based on the number of DET clock gater circuits in the series that are in a particular mode.
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