Semiconductor device and method of manufacturing the same

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United States of America Patent

PATENT NO 10121894
APP PUB NO 20180026134A1
SERIAL NO

15649984

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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In an LDMOS having an element isolation region of an STI structure, there is prevented an occurrence of insulation breakdown which might be caused when electrons generated in a semiconductor substrate near an edge portion of a bottom face of the element isolation region are poured into a gate electrode. Immediately over an upper surface of an offset region adjacent to the element isolation region embedded in a main surface of the semiconductor substrate between a source region and a drain region, there is provided a trench penetrating a silicon film forming the gate electrode. As a consequence, the silicon film and a metal film for filling the trench form the gate electrode.

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Patent Owner(s)

Patent OwnerAddress
RENESAS ELECTRONICS CORPORATION2-24 TOYOSU 3-CHOME KOTO-KU TOKYO 135-0061

International Classification(s)

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  • 2017 Application Filing Year
  • H01L Class
  • 30754 Applications Filed
  • 25260 Patents Issued To-Date
  • 82.14 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances2017201820192020202120222023202420250255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Eikyu, Katsumi Tokyo, JP 41 251
Sakai, Atsushi Tokyo, JP 184 1278

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Patent Citation Ranking

  • 1 Citation Count
  • H01L Class
  • 23.71 % this patent is cited more than
  • 7 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges3689997611243481558461392216162801 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +05001000150020002500300035004000450050005500600065007000750080008500900095001000010500

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