Semiconductor device and method of manufacturing the same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 6, 2018
Grant Date -
Jan 25, 2018
app pub date -
Jul 14, 2017
filing date -
Jul 20, 2016
priority date (Note) -
In Force
status (Latency Note)
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Abstract
In an LDMOS having an element isolation region of an STI structure, there is prevented an occurrence of insulation breakdown which might be caused when electrons generated in a semiconductor substrate near an edge portion of a bottom face of the element isolation region are poured into a gate electrode. Immediately over an upper surface of an offset region adjacent to the element isolation region embedded in a main surface of the semiconductor substrate between a source region and a drain region, there is provided a trench penetrating a silicon film forming the gate electrode. As a consequence, the silicon film and a metal film for filling the trench form the gate electrode.
First Claim
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
RENESAS ELECTRONICS CORPORATION | 2-24 TOYOSU 3-CHOME KOTO-KU TOKYO 135-0061 |
International Classification(s)

- 2017 Application Filing Year
- H01L Class
- 30754 Applications Filed
- 25260 Patents Issued To-Date
- 82.14 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Eikyu, Katsumi | Tokyo, JP | 41 | 251 |
# of filed Patents : 41 Total Citations : 251 | |||
Sakai, Atsushi | Tokyo, JP | 184 | 1278 |
# of filed Patents : 184 Total Citations : 1278 |
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Patent Citation Ranking
- 1 Citation Count
- H01L Class
- 23.71 % this patent is cited more than
- 7 Age
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