Power transistor having perpendicularly-arranged field plates and method of manufacturing the same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 13, 2019
Grant Date -
Jan 25, 2018
app pub date -
Jul 19, 2017
filing date -
Jul 20, 2016
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A semiconductor device in a semiconductor substrate having a first main surface includes a transistor array and a termination region. The transistor array includes a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel in the body region. The body region and the drift zone are disposed along a first horizontal direction between the source region and the drain region. The transistor array further includes first field plate trenches in the drift zone. A longitudinal axis of the first field plate trenches extends in the first horizontal direction. The semiconductor device further includes a second field plate trench, a longitudinal axis of the second field plate trench extending in a second horizontal direction perpendicular to the first direction.
First Claim
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
INFINEON TECHNOLOGIES AG | CAMPBELL 1-15 NAUBIBERG GERMANY NEUBIBERG BAVARIA |
International Classification(s)

- 2017 Application Filing Year
- H01L Class
- 30754 Applications Filed
- 25260 Patents Issued To-Date
- 82.14 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Meiser, Andreas Peter | Sauerlach, DE | 26 | 561 |
# of filed Patents : 26 Total Citations : 561 | |||
Schloesser, Till | Munich, DE | 116 | 1665 |
# of filed Patents : 116 Total Citations : 1665 |
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- 0 Citation Count
- H01L Class
- 0 % this patent is cited more than
- 6 Age
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