Low-resistive, CMOS-compatible, Au-free ohmic contact to N—InP
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United States of America Patent
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Mar 13, 2018
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app pub date -
Jul 21, 2016
filing date -
Jul 21, 2016
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Abstract
A device includes an n-doped InP layer and an ohmic contact, in contact with the n-doped InP layer. The ohmic contact includes an annealed stack of at least three, or preferably four alternating layers of Si and Ni, such that: (i) the n-doped InP layer and one of the layers of the stack in contact with the n-doped InP layer are at least partly intermixed; and (ii) any two adjacent layers of the stack are at least partly intermixed. Related fabrication methods are also disclosed.
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