MEMORY DEVICE
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United States of America Patent
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app pub date -
Jan 25, 2017
filing date -
Jul 20, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
A memory device includes gate electrode layers stacked on an upper surface of a substrate and each including a plurality of unit electrodes extending in a first direction, and a plurality of connecting electrodes connecting the unit electrodes to each other. The memory device also includes channel structures extending through the gate electrode layers in a direction perpendicular to the upper surface of the substrate, first common source lines extending in the first direction and interposed between the unit electrodes, and second common source lines extending in the first direction between the first common source lines and each having a first line and a second line separated from each other in the first direction by the connecting electrodes.
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Patent Citation Ranking
- 21 Citation Count
- H01L Class
- 95.06 % this patent is cited more than
- 7 Age