Memory device
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United States of America Patent
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Apr 24, 2018
Issued Date -
N/A
app pub date -
Dec 12, 2016
filing date -
Jul 19, 2016
priority date (Note) -
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Abstract
In one embodiment, the semiconductor device includes a stack of alternating first interlayer insulating layers and gate electrode layers on a substrate. At least one of the gate electrode layers has a first portion and a second portion. The second portion forms an end portion of the at least one gate electrode layer, and a bottom surface of the second portion is at a lower level than a bottom surface of the first portion. A contact plug extends from the second portion.
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