Vertically stacked FinFET fuse
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United States of America Patent
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Aug 21, 2018
Grant Date -
Jan 25, 2018
app pub date -
Jul 27, 2017
filing date -
Jul 21, 2016
priority date (Note) -
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Abstract
A semiconductor structure including a stacked FinFET fuse is provided in which the stacked FinFET fuse includes a plurality of vertically stacked and spaced apart conductive semiconductor fin portions and a doped epitaxial semiconductor material structure located on exposed surfaces of each conductive semiconductor fin portion of the vertical stack. In the FinFET fuse, a topmost surface of a bottom doped epitaxial semiconductor material structure is merged to a bottommost surface of an overlying doped epitaxial semiconductor material structure.
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