Three-dimensional semiconductor device including integrated circuit, transistors and transistor components and method of fabrication
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United States of America Patent
Stats
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Oct 22, 2019
Grant Date -
Jan 25, 2018
app pub date -
Jul 19, 2017
filing date -
Jul 19, 2016
priority date (Note) -
In Force
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Abstract
A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the surface on a first plane substantially parallel to the substrate surface. A second semiconductor device has a second electrical contact and is formed in a second area of the surface on a second plane substantially parallel to the surface and vertically spaced from the first plane in a direction substantially perpendicular to the surface. A first electrode structure includes opposing top and bottom surfaces substantially parallel to the substrate surface, and a sidewall connecting the top and bottom surfaces such that the electrode structure forms a three dimensional electrode space. A conductive fill material is provided in the electrode space, and a dielectric layer electrically separates the conductive fill material into a first electrode electrically connected to the first contact of the first semiconductor device and a second electrode electrically connected to the second semiconductor device and electrically insulated from the first electrode. A first circuit terminal extends vertically from the top or bottom surface of the electrode structure and is electrically connected to the first electrode.

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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
- TOKYO ELECTRON LIMITED
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
deVilliers, Anton | Clifton Park, US | 84 | 1044 |
Smith, Jeffrey | Clifton Park, US | 263 | 2937 |
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