Integrated circuit with NMOS and PMOS transistors having different threshold voltages through channel doping and gate material work function schemes
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United States of America Patent
Stats
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May 29, 2018
Issued Date -
N/A
app pub date -
Jul 18, 2017
filing date -
Jul 22, 2016
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An integrated circuit comprising: first to third nMOS transistors with different threshold voltages, and first to third pMOS transistors with different threshold voltages, the nMOS transistors having channel regions made of silicon subjected to tensile stress and/or said pMOS transistors having channel regions made of SiGe subjected to compressive stress; a first well and a second well that are arranged underneath the nMOS transistors and underneath the pMOS transistors, respectively, with one and the same doping; two nMOS gate stacks comprising one and the same material, two of the nMOS gate stacks comprising materials having separate work functions, an nMOS gate stack having one and the same material as a pMOS gate stack, with the equation: Gp*Vdds−Gn*Gnds=Sn*|σn|+Sp*(|σp|−1.65*109)−VarCais+K.
First Claim
Other Claims data not available
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International Classification(s)
- 2017 Application Filing Year
- H01L Class
- 30754 Applications Filed
- 25260 Patents Issued To-Date
- 82.14 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 1 Citation Count
- H01L Class
- 23.71 % this patent is cited more than
- 7 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Nov 29, 2025 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Nov 29, 2029 |
