Reducing wafer warpage during wafer processing

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 10026698
APP PUB NO 20180025995A1
SERIAL NO

15722524

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Abstract

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According to one embodiment, there is provided a manufacturing method of a semiconductor device. The method includes forming a first guard ring around a first chip region on a semiconductor wafer. The method includes forming a second guard ring around a second chip region on the semiconductor wafer. The method includes mechanically connecting the first guard ring with the second guard ring through a joist structure.

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Patent Owner(s)

Patent OwnerAddress
KIOXIA CORPORATION1-21 SHIBAURA 3-CHOME MINATO-KU TOKYO 108-0023

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Konomi, Kenji Nagoya, JP 16 110

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