Semiconductor package structure and manufacturing method thereof
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United States of America Patent
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Jun 12, 2018
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N/A
app pub date -
Dec 7, 2016
filing date -
Jul 25, 2016
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Abstract
A semiconductor package structure includes a redistribution layer (RDL), a chip, a plurality of interconnecting bumps and an encapsulant. The redistribution layer has a first surface and a second surface opposite to each other. The chip is disposed over the redistribution layer with a plurality of contact pads facing the first surface and electrically connected to the redistribution layer. The interconnecting bumps are disposed over the first surface and electrically connected to the redistribution layer. The encapsulant is disposed over the first surface of the redistribution layer, and the encapsulant encloses the chip and surrounds lateral walls of the interconnecting bumps.
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