Formation of liner and metal conductor
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United States of America Patent
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Apr 30, 2019
Grant Date -
Jan 25, 2018
app pub date -
Feb 21, 2017
filing date -
Jul 22, 2016
priority date (Note) -
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Abstract
An integrated circuit device includes a substrate including a dielectric layer patterned with a set of conductive line trenches, each conductive line trench having parallel vertical sidewalls and a horizontal bottom. A liner which is an alloy of a first metal and a selected element formed at interfaces of the metal layer and a surface of the dielectric and is created by an anneal and reflow process. The first metal having a first conductivity in a pure form. A second metal layer fills the set of conductive line trenches, the second metal having a second conductivity higher than the first conductivity.
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