Shared error detection and correction memory
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United States of America Patent
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Issued Date -
Jan 25, 2018
app pub date -
Jul 22, 2016
filing date -
Jul 22, 2016
priority date (Note) -
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Abstract
Apparatuses and methods for an interface chip are described. An example apparatus includes a first chip. The first chip includes, on a single semiconductor substrate, first terminals, circuit groups, and terminal groups corresponding to the circuit groups, each of the circuit groups including circuit blocks. A control circuit in the first chip selects one of the circuit groups and electrically couples the first terminals to the circuit blocks of the selected circuit group. Second terminals are included in each of the terminal groups. A number of all of the second terminals in each of the terminal groups is smaller than a number of all of the circuit blocks in the corresponding circuit group. The first chip further includes, for example, a remapping circuit.
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