Semiconductor devices having a refresh operation
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United States of America Patent
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Mar 13, 2018
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N/A
app pub date -
Feb 8, 2017
filing date -
Jul 25, 2016
priority date (Note) -
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Abstract
A semiconductor device includes a first row address generation circuit and a second row address generation circuit. The first row address generation circuit generates a first row address for refreshing memory cells connected to word lines included in a first up block and a second up block from a refresh command and an active signal in response to a period selection signal and a first period signal. The second row address generation circuit generates a second row address for refreshing memory cells connected to word lines included in a first down block and a second down block from the refresh command and the active signal in response to the period selection signal and a second period signal.
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