REFRESH CONTROL CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
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United States of America Patent
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app pub date -
Nov 3, 2016
filing date -
Jul 22, 2016
priority date (Note) -
Abandoned
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Abstract
A refresh control circuit may be provided. The refresh control circuit may include a row address control circuit configured to reset a corresponding block control signal among a plurality of block control signals, based on a stop signal for stopping a refresh operation of a specific block being enabled. The refresh control circuit may include a refresh enable control circuit configured to combine the plurality of block control signals and a plurality of refresh control signals, and output a refresh enable signal.
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