Semiconductor device including metal-oxide-semiconductor disposed in a column decoder region
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United States of America Patent
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Jun 12, 2018
Issued Date -
Jan 25, 2018
app pub date -
Apr 12, 2017
filing date -
Jul 22, 2016
priority date (Note) -
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Abstract
A semiconductor device may be provided. The semiconductor device may include a first power line located in a memory cell array region. The semiconductor device may include a second power line located in a column decoder region. The semiconductor device may include a third power line formed in a layer different from the first power line and the second power line, configured to couple the first power line to the second power line. The semiconductor device may include a metal-oxide-semiconductor (MOS) capacitor located below the third power line.
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