Staged power on/off sequence at the I/O phy level in an interchip interface
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United States of America Patent
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Jan 26, 2021
Grant Date -
Jan 25, 2018
app pub date -
Jul 21, 2016
filing date -
Jul 21, 2016
priority date (Note) -
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Abstract
A method, system, and/or computer program product controls transitions from a first bandwidth to a second bandwidth in a bus within a multi-processor computer. A bus controller predicts a bandwidth transition requirement for a bus in a multi-processor computer, and transitions the bus from a first bandwidth to a second bandwidth based on the predicted bandwidth transition requirement. The bus controller checks an actual transitioning requirement of the bus in the computer, such that the bus controller checks the actual transitioning requirement for the bus at each occurrence of a predefined stage of operation of one or more processor processors in the computer. In response to the actual transitioning requirement matching the predicted bandwidth transition requirement, the bus controller directions a continuation of the transitioning of the bus from the first bandwidth to the second bandwidth.
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