Decoder using low-density parity-check code and memory controller including the same
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United States of America Patent
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Jun 18, 2019
Grant Date -
Jan 25, 2018
app pub date -
Jul 18, 2017
filing date -
Jul 19, 2016
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Abstract
A decoder includes a channel mapper configured to generate a plurality of channel reception values based on hard decision information and soft decision information, a strong error detector configured to determine whether a strong error has occurred using a plurality of check node messages and the channel reception values and to correct the channel reception values according to a determination result to produce corrected channel reception values, a variable node unit configured to generate a plurality of variable node messages using the check node messages and the corrected channel reception values, and a check node unit configured to generate the check node messages using the variable node messages. The variable node unit includes a plurality of variable nodes and the check node unit includes a plurality of check nodes.
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