TEST PATTERN COUNT REDUCTION FOR TESTING DELAY FAULTS
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United States of America Patent
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Sep 29, 2017
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Mar 20, 2015
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One or more non-transitory computer-readable storage media is provided, the storage media is configured to store instructions that, when executed by a processor included in an apparatus, cause the processor to perform operations comprising: identify a plurality of transition faults that is to possibly occur in a circuit; generate a plurality of modified fault expressions, at least one of the plurality of modified fault expressions being associated with a corresponding transition fault of the plurality of transition faults; identify a plurality of test patterns, wherein at least one test pattern of the plurality of test patterns results in satisfiability of corresponding one or more of the plurality of modified fault expressions; and output the plurality of test patterns to a testing arrangement to test the circuit
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