Signal pin arrangement for multi-device power module
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United States of America Patent
Stats
-
Nov 27, 2018
Grant Date -
Jan 25, 2018
app pub date -
Jul 20, 2016
filing date -
Jul 20, 2016
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A power module provides one or more power transistors and support elements in a card shape. The pins/terminals for signal-level input/outputs (e.g., gate drive, current sensor, and temperature sensor signals) are arranged in two parallel layers. The power terminals (e.g., positive and negative bus, and output junction of a phase leg) are preferably arranged in just one of the layers. The signal pins are spaced both laterally across a long edge of the power module and transversely to the edge direction, so that the minimum spacings (i.e., clearances) can be achieved while shortening the lateral length of the edge(s) of the power module. Preferably, the signal pins belonging to an individual power transistor (e.g., an IGBT or MOSFET) are distributed between the two layers so that corresponding signal loops can be magnetically decoupled from the power terminal loop.
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Cited Art Landscape
Patent Citation Ranking
- 4 Citation Count
- H02M Class
- 19.31 % this patent is cited more than
- 7 Age
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| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | May 27, 2026 |
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