Apparatus for design for testability of multiport register arrays
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United States of America Patent
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Apr 10, 2018
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app pub date -
Jul 12, 2016
filing date -
Jul 12, 2016
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Abstract
In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.
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