MULTI-LEVEL CLOCK GATE CONTROLS TO ADDRESS SCAN MODE POWER DROOP AND VOLTAGE BUMP REQUIREMENT
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Jul 14, 2016
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Jul 14, 2016
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Embodiments described herein provide a method and apparatus for multi-level clock gate control for testing electronic devices. The method begins when the number of clock gate controls from root level to the last leaf level are identified and then ranked from the root to last leaf level. A number of test enable commands for testing at least one block of an electronic device are determined. These commands selectively connect and disconnect the test enable commands based on the ranked clock gate levels. The apparatus includes a chain of at least two uncompressed flip-flops with additional flip-flops added to provide multi-level clock gate control during testing. An OR gate in communication with each added flip-flop provides the logic functions to selectively connect and disconnect the test enable command A decompressor and a compressor is in communication with the chain of at flip-flops and the OR gates.
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