Programmable bulk FinFET antifuses
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United States of America Patent
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Oct 23, 2018
Grant Date -
Jan 18, 2018
app pub date -
Jul 18, 2016
filing date -
Jul 18, 2016
priority date (Note) -
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Abstract
An antifuse device includes a gate structure formed on a substrate including first spacers formed in an upper portion and a conductive material formed in a lower portion below the first spacers. Two conductive regions are disposed adjacent to the gate structure and on opposite sides of the gate structure. A dielectric barrier is formed between the conductive material and each of the conductive regions such that a dual antifuse is formed across the dielectric barrier between the conductive material and the conductive regions on each side of the gate structure.
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