Method for manufacturing three-dimensional semiconductor integrated circuit device
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United States of America Patent
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Jun 25, 2019
Grant Date -
Jan 18, 2018
app pub date -
Dec 2, 2016
filing date -
Jul 15, 2016
priority date (Note) -
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Abstract
A semiconductor integrated circuit device may include an isolating layer, a buried gate, source and drain regions, a dielectric layer having a high dielectric constant and an insulating interlayer. The isolating layer may be formed on a semiconductor substrate to define an active region. The buried gate may be formed in the active region of the semiconductor substrate. The source and drain regions may be formed in the active region at both sides of the buried gate. The dielectric layer may be configured to surround the source and drain regions. The insulating interlayer may be formed on the dielectric layer.
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