Chip scale package and related methods
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United States of America Patent
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Sep 18, 2018
Grant Date -
Jan 18, 2018
app pub date -
Aug 11, 2017
filing date -
Jul 14, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
Implementations of semiconductor packages may include: a die coupled to a glass lid; one or more inner walls having a first material coupled to the die; an outer wall having a second material coupled to the die; and a glass lid coupled to the die at the one or more inner walls and at the outer wall; wherein the outer wall may be located at the edge of the die and the glass lid and the one or more inner walls may be located within the perimeter of the outer wall at a predetermined distance from the perimeter of the outer wall; and wherein a modulus of the first material may be lower than a modulus of the second material.
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