Memory device
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United States of America Patent
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Oct 16, 2018
Grant Date -
Jan 18, 2018
app pub date -
Apr 7, 2017
filing date -
Jul 14, 2016
priority date (Note) -
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Abstract
A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of vertical holes extending in a direction perpendicular to the upper surface of the substrate to penetrate through the gate structure, and a plurality of vertical structures in the plurality of vertical holes, respectively, each vertical structure of the plurality of vertical structures including an embedded insulating layer, and a plurality of channel layers separated from each other, the plurality of channel layers being outside the embedded insulating layer.
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