Self-aligned 3-D epitaxial structures for MOS device fabrication

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United States of America Patent

PATENT NO 11171058
APP PUB NO 20180019170A1
SERIAL NO

15668288

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Abstract

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Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

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Patent Owner(s)

  • INTEL CORP.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Aubertine, Daniel B North Plains, US 26 702
Ghani, Tahir Portland, US 756 7842
Glass, Glenn A Portland, US 182 5017
Murthy, Anand S Portland, US 351 6235
Thareja, Gaurav Hillsboro, US 75 903

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