Semiconductor test device and semiconductor test method
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United States of America Patent
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May 15, 2018
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app pub date -
Feb 17, 2017
filing date -
Jul 15, 2016
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Abstract
A semiconductor test device and a semiconductor test method are disclosed. A semiconductor test device may include a DQ signal receiver, a test mode register set signal processor, and a test mode command generator. The DQ signal receiver may receive a first DQ signal through a first DQ pin. The test mode register set signal processor may receive a test mode register set signal in response to the first DQ signal, and may output a test mode register set pulse signal. The test mode command generator may generate a test mode command corresponding to an input address in response to the test mode register set pulse signal.
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