Replicating test case data into a cache and cache inhibited memory
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United States of America Patent
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Aug 21, 2018
Grant Date -
Jan 18, 2018
app pub date -
Jul 12, 2016
filing date -
Jul 12, 2016
priority date (Note) -
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Abstract
Data is replicated into a memory cache and cache inhibited memory in data segments with segment size that provides non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries allows replicated testing of the memory cache and cache inhibited memory while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases generated for cacheable memory to be replicated and used for cache inhibited memory. The processor can then use a single test replicated in this manner by branching back and using the next slice of the replicated test data in the memory cache and cache inhibited memory.
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