Method and apparatus for reducing constraints during rewind structural verification of retimed circuits
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United States of America Patent
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Nov 26, 2019
Grant Date -
Jan 18, 2018
app pub date -
Sep 28, 2017
filing date -
Mar 24, 2016
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Abstract
A method for performing a rewind functional verification includes identifying state variables that model a number of registers on each edge of a retiming graph for an original design and a retimed design. Random variables are identified that model retiming labels representing a number and a direction of a register movement relative to a node on a retiming graph for the retimed design. A retiming constraint is identified for each edge on the retiming graph for the retimed design, wherein the retiming constraint reflects a relationship between the state variables and the random variables. A random variable that models a retiming label at a source of an edge is recursively substituted for a random variable that models a retiming label at a sink of the edge when a number of registers on the edge is unchanged after register retiming.
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