METHOD AND APPARATUS FOR DETECTING AND RESOLVING BUS HANG IN A BUS CONTROLLED BY AN INTERFACE CLOCK
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United States of America Patent
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N/A
Issued Date -
Jan 18, 2018
app pub date -
Jul 13, 2016
filing date -
Jul 13, 2016
priority date (Note) -
Published
status (Latency Note)
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Abstract
Systems and methods are disclosed for resolving bus hang in a computing device. An exemplary system comprises a bus operating in accordance with an interface clock, and a controller in communication with the bus. The controller comprises a finite state machine, where the finite state machine is configured to receive a clock signal from the interface clock and a command signal originating external to the controller. The controller also comprising hang detection logic configured to receive one or more signals that the finite state machine is active, monitor the interface clock, and generate an event notification in response to the interface clock turning off while the finite state machine is active. The controller further comprises a trap handler in communication with the hang detection logic, the trap handler configured to send an interrupt in response to the event notification.
First Claim
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