Command arbitration for high speed memory interfaces
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United States of America Patent
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Jun 16, 2020
Grant Date -
Jan 18, 2018
app pub date -
Jul 15, 2016
filing date -
Jul 15, 2016
priority date (Note) -
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Abstract
In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data processing system includes a memory accessing agent for providing memory accesses requests, a memory system, and the memory controller coupled to the memory accessing agent and the memory system.
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