System, Apparatus And Method For Secure Monotonic Counter Operations In A Processor
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United States of America Patent
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Jan 18, 2018
app pub date -
Jul 14, 2016
filing date -
Jul 14, 2016
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Abstract
In one embodiment, an apparatus includes: at least one core to execute instructions, the at least one core formed on a semiconductor die; a first memory formed on the semiconductor die, the first memory comprising a non-volatile random access memory, the first memory to store a first entry to be a monotonic counter, the first entry including a value field and a status field; and a control circuit, wherein the control circuit is to enable access to the first entry if the apparatus is in a secure mode and otherwise prevent the access to the first entry. Other embodiments are described and claimed.
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