Apparatus and method for low power low latency high capacity storage class memory
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United States of America Patent
Stats
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Dec 8, 2020
Grant Date -
Jan 18, 2018
app pub date -
Sep 26, 2017
filing date -
Oct 8, 2012
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A method and a storage system are provided for implementing enhanced solid state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing Dynamic Random Access Memory (DRAM), and at least one 5 non-volatile memory, for example, Phase Change Memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND Flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size.
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International Classification(s)
- 2017 Application Filing Year
- G06F Class
- 61356 Applications Filed
- 46481 Patents Issued To-Date
- 75.76 % Issued To-Date
Cited Art Landscape
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- 0 Citation Count
- G06F Class
- 0 % this patent is cited more than
- 5 Age
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