Delaying purging of structures associated with address translation
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 8, 2019
Grant Date -
Jan 18, 2018
app pub date -
Jul 18, 2016
filing date -
Jul 18, 2016
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Virtual machine purging of structures associated with address translation is delayed. A host logical processor executing on a physical processor issues a local purge request to purge entries of a structure associated with address translation. The structure associated with address translation includes one or more host entries for the host logical processor and one or more guest entries for a guest virtual processor running on the physical processor. Based on issuing the local purge request, an indicator is set to control purging of the one or more guest entries of the structure associated with address translation. Further, purging of the one or more guest entries of the guest virtual processor is delayed for consideration of purging at dispatch of the guest virtual processor.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully