Efficiency for coordinated start interpretive execution exit for a multithreaded processor
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United States of America Patent
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Feb 2, 2021
Grant Date -
Jan 18, 2018
app pub date -
Sep 27, 2017
filing date -
Oct 20, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
A system and method of implementing a wait state for a plurality of threads executing on a computer processor core of the processor. The processor is configured to execute instruction streams by the plurality of threads, wherein the plurality of threads includes a first thread and a set of remaining threads and determine that the first thread has entered a first wait state loop. The processor is also configured to determine that any of the set of remaining threads has not entered a corresponding wait state loop and remain by the first thread in the first wait state loop until each of the set of remaining threads has entered the corresponding wait state loop.
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