Memory controller arbiter with streak and read/write transaction management
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United States of America Patent
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Sep 3, 2019
Grant Date -
Jan 18, 2018
app pub date -
Sep 22, 2016
filing date -
Jul 15, 2016
priority date (Note) -
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Abstract
In one form, an apparatus includes a memory controller. The memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter picks the memory access requests from the command queue based on a plurality of criteria, and provides picked memory access requests to a memory channel. The arbiter includes a streak counter for counting a number of consecutive memory access requests of a first type that the arbiter picks from the command queue. When the streak counter reaches a threshold, the arbiter suspends picking requests of the first type and picks at least one memory access request of a second type. The arbiter provides the at least one memory access request of the second type to the memory channel.
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