Memory controller for performing write transaction with stall when write buffer is full and abort when transaction spans page boundary
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United States of America Patent
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Oct 23, 2018
Grant Date -
Jan 18, 2018
app pub date -
Jul 12, 2016
filing date -
Jul 12, 2016
priority date (Note) -
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Abstract
A memory controller receives first and second write transactions from a processor and stores write data in a memory. The memory controller includes an address comparison circuit, a buffer, a level control circuit, a command generator, and a control circuit. The address comparison circuit compares second and third addresses and outputs first and second write data when the second and third addresses are consecutive. The buffer stores the first and second write data and outputs buffered data based on a control signal. The level control circuit compares a size of the buffered data with a threshold size and the size of the buffer. The command generator causes a write transaction to be executed based on the comparison results, rather than having the processor initiate the transaction, which reduces the load on the processor, and the buffered write data is stored in the memory.
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