MEMORY SYSTEM
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United States of America Patent
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app pub date -
Mar 28, 2017
filing date -
Jul 15, 2016
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Abstract
Provided herein is a memory device including a memory cell array, a peripheral circuit configured to perform a first operation for the memory cell array, and a control circuit configured to generate an operation status code and output the operation status code. The first operation includes a plurality of second operations that are successively performed. The operation status code indicates, among the plurality of second operations, a current operation that is being performed by the peripheral circuit.
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