Two stage command buffers to overlap IOMMU map and second tier memory reads
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United States of America Patent
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May 21, 2019
Grant Date -
Jan 18, 2018
app pub date -
Sep 16, 2016
filing date -
Jul 14, 2016
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Abstract
IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.
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